1. Field of the Invention
The present invention relates to a solid-state imaging device, and more particularly relates to a charge coupled device (CCD) type solid-state imaging device and a method for manufacturing the same.
2. Description of Related Art
In recent years, demands for solid-state imaging devices have been increasing as imaging devices for digital still cameras and digital video cameras. Further, since there is a request for portable terminal devices such as a cellphone additionally to have a camera function, the demands for solid-state imaging devices have been increasing also for the imaging devices of such portable terminal devices. Furthermore, in order to obtain a high quality image, the number of pixels in a solid-state imaging device has been increased year by year. In addition, in line with the request for lower power consumption of digital still cameras, digital video cameras and portable terminal devices, solid-state imaging devices with lower power consumption also have been demanded.
Referring now to FIGS. 5 to 8, a conventional solid-state imaging device is described below. Firstly, the schematic configuration of the conventional solid-state imaging device is described. FIG. 5 is a plan view showing the schematic configuration of a conventional CCD type solid-state imaging device. As shown in FIG. 5, the CCD type solid-state imaging device has a semiconductor substrate 101. The semiconductor substrate 101 is provided with a plurality of two-dimensionally arranged light-receptive portions 102, a vertical transfer portion (vertical CCD) 103 arranged along each column of the light-receptive portions 102 in the vertical direction and a horizontal transfer portion (horizontal CCD) 104 provided adjacent to the final row of the light-receptive portions 102. The light-receptive portions 102 are photodiodes, which store electric charge in accordance with the intensity of the received light. One light-receptive portion 102 and a part of the adjacent vertical CCD 103 make up one pixel 108.
As shown by arrows of FIG. 5, electric charge stored in the light-receptive portions 102 is read out and transferred in the vertical direction by the vertical CCD 103. The electric charge transferred by the vertical CCD 103 is transferred by the horizontal CCD 104 in the horizontal direction, is amplified by an amplifier 105 and is output to the outside.
Further, as shown in FIG. 5, a drain region 107 is provided across a barrier region 106 on the side of the horizontal CCD 104 that is not adjacent to the vertical CCD 103 (see JP H10(1998)-50975 A, for example). The barrier region 106 is a potential barrier, which lets only surplus electric charge of the horizontal CCD pass therethrough. Therefore, the surplus of the electric charge transferred to the horizontal CCD 104 is discharged to the drain region 107.
Next, specific configurations of the vertical CCD 103, the horizontal CCD 104 and the drain region 107 are described below, with reference to FIGS. 6 and 7. FIG. 6 is an enlarged plan view of a part of the conventional CCD type solid-state imaging device of FIG. 5. FIG. 7 shows the configuration of a part of the conventional CCD type solid-state imaging device in cross section. The cross section of FIG. 7 is taken along the line A-A′ of FIG. 6, which illustrates the lines appearing in the cross section only.
As shown in FIG. 6, each of the vertical CCD 103 and the horizontal CCD 104 is configured with a channel region 109 serving as a transfer path of the electric charge and a two-layered transfer electrode. Herein, in FIG. 6, a transfer electrode in the first layer is illustrated with hatching. More specifically, the vertical CCD 103 is made up of a portion 109a of the channel region 109 extending in the vertical direction, a first-layer vertical transfer electrode 112 and a second-layer vertical transfer electrode 113. The vertical CCD 103 is four-phase driven. The horizontal CCD 104 is made up of a portion 109b of the channel region 109 extending in the horizontal direction, a first-layer horizontal transfer electrode 110 and a second-layer horizontal transfer electrode 111. The horizontal CCD 104 is two-phase driven.
As shown in FIG. 7, the semiconductor substrate 101 is a n-type silicon substrate, on which a p-type well 114 is formed. The channel region 109 is formed on the p-type well 114. The channel region 109, the barrier region 106 and the drain region 107 are n-type diffusion layers, and a gate insulation film 115 is formed on these regions. Further, on the side opposite to the channel region 109 with reference to the drain region 107, an insulation film 116 is formed to have a larger thickness than that of the gate insulation film 115. Herein, the insulation film 116 is omitted in FIGS. 5 and 6. The insulation film 116 functions as isolation from a peripheral circuit such as a protective circuit (not illustrated), and the insulation film 116 actually is formed so as to surround the whole major portion including the plurality of light-receptive portions 102, the vertical CCD 103, the horizontal CCD 104, the barrier region 106, the drain region 107 and the like.
Further, as shown in FIGS. 6 and 7, the horizontal transfer electrodes 110 and 111 are formed so as to overlap with the barrier region 106, the drain region 107 and the insulation film 116 along the vertical direction. Moreover, as shown in FIG. 7, the horizontal transfer electrode 110 (and 111) is covered with an insulation film 119. Voltage is applied to the horizontal transfer electrode 110 via a contact 117 provided in the insulation film 119 and an aluminum wiring 118 provided on the contact 117. The contact 117 is provided at a position overlapping with the insulation film 116 serving as isolation. This is because, if the contact 117 is formed at a region overlapping with the gate insulation film 115, the application of voltage might cause dielectric breakdown in the gate insulation film 115.
Now referring to FIG. 8, a method of manufacturing the conventional solid-state imaging device shown in FIGS. 5 to 7 is described below. FIG. 8 shows the manufacturing method of the conventional solid-state imaging device in cross section, in which FIGS. 8A to 8E show a series of major manufacturing steps. Herein, FIG. 8 shows major manufacturing steps concerning a cross-sectional portion taken along the line A-A′ of FIG. 6, and these drawings illustrate lines appearing on the cross section only.
Firstly, as shown in FIG. 8A, a silicon oxide film (SiO2) 120 and a silicon nitride film (SiN) 121 are formed successively on the top of a semiconductor substrate 101. Following this, a resist pattern (not illustrated) having an aperture corresponding to the formation region of an insulation film 116 serving as isolation is formed. Etching is applied thereto so as to remove a part of the silicon nitride film 121.
Next, as shown in FIG. 8B, the insulation film 116 serving as isolation is formed by local oxidation of silicon (LOCOS). More specifically, thermal oxidation is performed so as to grow a portion of the silicon oxide film 120 that is not covered with the silicon nitride film 121, so that the insulation film 116 serving as isolation is formed. At this time, a portion of the silicon oxide film 120 that is covered with the silicon nitride film 121 becomes a gate insulation film 115. After that, the resist pattern is removed, and a p-type impurity (e.g., arsenic) is ion-implanted to the semiconductor substrate 101, whereby a p-type well 114 is formed.
Next, as shown in FIG. 8C, after the silicon nitride film 121 is completely removed, a resist pattern 122 having an aperture corresponding to the formation region of a drain region 107 is formed on the semiconductor substrate 101. At this time, the insulation film 116 serving as isolation is covered with the resist pattern 122. Following this, phosphorus (P) as impurity is ion-implanted, whereby the drain region 107 is formed. The ion-implantation in this step is performed under the conditions of the implantation energy (acceleration voltage) of 170 keV and the dose of 1.0×1013 ions/cm2, for example. Thereafter, the resist pattern 122 is removed.
Next, as shown in FIG. 8D, a channel region 109 and a barrier region 106 are formed, and thereafter a first-layer horizontal transfer electrode 110 is formed. More specifically, the channel region 109 and the barrier region 106 are formed as follows. Firstly, a resist pattern having apertures corresponding to the formation regions of the channel region 109 and the barrier region 106 is formed, followed by ion-implantation of a n-type impurity (e.g., phosphors). Then, after this resist pattern is removed, a new resist pattern having an aperture corresponding to the formation region of the barrier region 106 only is formed, followed by ion-implantation of a p-type impurity (e.g., boron). The first-layer horizontal transfer electrode 110 can be formed by deposition of a polysilicon film, formation of a resist pattern and etching.
Next, as shown in FIG. 8E, a silicon oxide film 119a is formed on the first-layer horizontal transfer electrode 110 by thermal oxidation. Following this, although not illustrated, a second-layer horizontal transfer electrode 111 is formed using polysilicon. Next, a silicon oxide film 119b is formed, and then a contact 117 and an aluminum wiring 118 are formed successively, whereby a solid-state imaging device can be obtained.
In the above-stated solid-state imaging device, as the number of pixels is increased, the number of the horizontal transfer electrodes is increased, so that the surplus electric charge amount is increased as well. Therefore, the discharging capability of the surplus electric charge by the drain region 107 should be improved. It can be considered that the discharging capability of the surplus electric charge by the drain region 107 can be improved by increasing an impurity density of the drain region 107, i.e., by increasing the dose of the ion-implantation for the drain region 107.
However, when the dose is increased, a semiconductor region (e.g., a source/drain region of a MOS transistor constituting a peripheral circuit such as a protective circuit), which can be formed by the same process as that for the drain region 107 before increasing the dose, has to be formed by a different process, and therefore the cost for a solid-state imaging device will be increased. Further, as the dose is increased, the dielectric breakdown strength (withstand voltage) of the gate insulation film 115 will be degraded. Therefore, there is a limit to the improvement of the discharging capability by increasing the impurity density of the drain region 107. For that reason, the capability of discharging surplus electric charge by the drain region 107 has been improved by enlarging the area of the drain region 107, more specifically, by enlarging the drain region 107 in the vertical direction.
However, when the drain region 107 is enlarged in the vertical direction (the lateral direction on the sheet of FIG. 7), the area of the drain region 107 contacting with the gate insulation film 115 increases accordingly, thus increasing a load capacity at the drain region 107. Further, the distance L (see FIG. 7) from the end of the drain region 107 on the horizontal CCD side to the contact 117 as a voltage application point also increases. As a result, power consumption at the drain region 107 will increase, which makes it difficult to satisfy the request of low power consumption for digital still cameras and the like.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a solid-state imaging device that suppresses an increase in power consumption at a drain region and to provide a method for manufacturing such a solid-state imaging device.